The present invention relates to a delay element for integrated circuits (ICs).
ICs generally require delay circuits to compensate for differences in operating speeds of elements so that data does not arrive at a location before the desired time. In a full custom IC, delay circuits, using for example variations in gate length and gate width could be designed so that slower gates could provide the desired delay. Alternatively, in a full custom design, resistor and capacitor arrangements could be used to introduce delay.
In a gate array environment, one does not have available components such as resistors and capacitors for constructing RC delay circuits. In a gate array environment, generally only pairs of p-channel and n-channel transistors formed beforehand on a semiconductor substrate are available for interconnection.
One example of a need for a delay element is where a register file is created in a gate array and it may be desirable to have the register file written at some time other than a time corresponding to the edges of the normal clock. A delay element may then be used to skew the timing of when the register is written.
In the past, to obtain the necessary delay time in the gate array environment, the signal transmission times through the logic gates are conventionally used. However, the delay from the input time to the output time of logic gate is very small. Therefore, a great number of logic gates must be connected in series in order to obtain the desired delay time. Variations on this logic gate approach could include connecting a group of p-channel transistors in series and a group of n-channel transistors in series and treating each connected group as a single transistor for use in constructing logic gates. However with this arrangement there may be floating nodes depending on circuit activity and environmental conditions. While the unknown voltage of the floating nodes would not be objectionable in many applications, in a delay element application, the delay time provided by the circuit may be affected by the voltage of the nodes. In a delay application where it is important to always know what the delay will be, it is desirable to have the nodes fully charge or discharge each time the element is switched. In another variation, only the gates of a number of otherwise unused transistors can be connected to increase capacitance at a circuit input and thereby provide delay. In still another variation metal capacitance may be added to slow down the delay gates.
All of the previously described approaches to delay elements will have certain undesired characteristics.
Thus a need exists for an efficient delay element that accurately provides a predetermined delay.